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| nt7704 240 output lcd segment/common driver 1v1.0 features (segment mode) ! shift clock frequency: 20 mhz (max.) (v dd = 5 v 10%) 12 mhz (max.) (v dd = 2.5v - 4.5v) ! adopts a data bus system ! 4-bit/8-bit parallel input modes are selectable with a mode (md) pin ! automatic transfer function with an enable signal ! automatic counting function when in "chip select" mode, which causes the internal clock to be stopped by automatically counting 240 bits of input data (common mode) ! shift clock frequency : 4.0 mhz (max.) ! built-in 240-bits bidirectional shift register (divisible into 120-bits x 2) ! available in a single mode (240-bits shift register) or in a dual mode(120-bits shift register x 2) 1. y1 y240 single mode 2. y240 y1 single mode 3. y1 y120, y121 y240 dual mode 4. y240 y121, y120 y1 dual mode the above 4 shift directions are pin-selectable (both for segment mode and common mode) ! supply voltage for lcd driver: 15.0 to 30.0 v ! number of lcd driver outputs: 240 ! low output impedance ! low power consumption ! supply voltage for the logic system: +2.5 to +5.5 v ! coms process ! package: gold bump die / 272 pin tcp(tape carrier package) ! not designed or rated as radiation hardened general description the nt7704 is a 240-bit output segment/common driver lsi suitable for driving large scale dot matrix lcd panels used by pda's, personal computers and work stations for example. through the use of cog technology, it is ideal for substantially decreasing the size of the frame section of the lcd module. the nt7704 is good as both a segment driver and as a common driver, and a low power consuming, high- precision lcd panel display can be assembled using the nt7704. in the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (md) pin. in the common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable. pin configuration nt7704 33 151 y 1 2 3 y 1 2 2 y 1 2 1 y 1 2 0 y 1 1 9 y 1 1 8 152 153 154 155 150 34 y 5 y 4 y 3 y 2 y 1 35 36 37 271 y 2 3 6 y 2 3 7 y 2 3 8 y 2 3 9 y 2 4 0 270 269 268 272 d u m m y d u m m y v 0 l v 0 l v 1 2 l v 4 3 l v 5 l v s s v d d s / c e i o 2 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 l p e i o 1 f r m d n c v s s x c k l / r d u m m y n c v 5 r v 1 2 r v 0 r v 0 r v 4 3 r d u m m y 1234567891011121314151617181920212223242526 27 28 29 30 31 32 d i s p o f f
nt7704 2 pad configuration nt7704 1 x alk_l x x alk_r x x dummy pad x 208 209 224 225 432 433 448 x block diagram 240 bits 4 level driver 240 bits level shifter 240 bits line latch/shift register y1 y2 y239 y240 v 43r v 12r v 0r level shifter fr dispoff active control eio 1 eio 2 control logic sp conversion & data control (4 to 8 or 8 to 8) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 l/r md s/c 8bits 2 data latch data latch control /8 /240 /240 v dd v ss v ss /16 /16 /16 /16 /16 lp xck v 5r v 5l v 12l v 0l v 43l nt7704 3 pad description pad no. designation i/o description 1 - 12 v 0l p power supply for lcd driver 13 - 20 v 12l p power supply for lcd driver 21 -28 v 43l p power supply for lcd driver 29 - 40 v 5l p power supply for lcd driver 41 - 66 v ss p ground (0v), these pads must be connected to each other 67 - 92 v dd p power supply for the logic system (+2.5 to +5.5v) 93 - 94 s/c i segment mode/common mode selection 95 - 97 eio 2 i/o input/output for chip select or data of the shift register 98, 99, 100 - 116, 117, 118 d0 - d6 i display data input for segment mode 119 - 121 d7 i display data input for segment mode/ dual mode data input 122 - 124 xck i display data shift clock input for segment mode 125 - 127 dispoff i control input for deselect output level 128 - 130 lp i latch pulse input/shift clock input for the shift register 131 - 133 eio 1 i/o input/output for chip select or data of the shift register 134 - 136 fr i ac-converting signal input for lcd driver waveform 137 - 139 l/r i display data shift direction selection 140 - 142 md i mode selection input 143 - 168 v ss p ground (0v), these pads must be connected to each other 169 - 180 v 5r p power supply for lcd driver 181 - 188 v 43r p power supply for lcd driver 189 - 196 v 12r p power supply for lcd driver 197 - 208 v 0r p power supply for lcd driver 209 - 448 y1 - y240 o lcd driver output nt7704 4 input / output circuits v dd v ss i input signal applicable pins l/r, s/c, d0 - d6, , lp, fr, md dispoff input circuit (1) v dd i v ss v ss input signal control signal applicable pins d7, xck input circuit (2) nt7704 5 v dd i/o v ss v ss input signal control signal applicable pins eio1, eio2 output signal control signal v ss v dd input / output circuit control signal 1 control signal 3 control signal 2 control signal 4 v0 v12 o v43 applicable pins y1 to y240 v5 v ss lcd driver output circuit nt7704 6 pad description segment mode symbol function v dd logic system power supply pin connects from +2.5 to +5.5v v ss ground pin connects to 0v v or , v ol v 12r , v 12l v 43r , v 43l v 5r , v 5l power supply pin for lcd driver voltage bias " normally, the bias voltage used is set by a resistor divider " ensure that the voltages are set such that v ss v 5 < v 43 < v 12 < v 0 " to further reduce the differences between the output waveforms of the lcd driver output pins y 1 and y 240, externally connect v ir and v il (i = 0, 12, 43, 5) d 0 - d 7 input pin for display data " in 4-bit parallel input mode, input data into the 4 pins d 0 - d 3 . connect d 4 - d 7 to v ss or v dd " in 8-bit parallel input mode, input data into the 8 pins d 0 - d xck clock input pin for taking display data " data is read on the falling edge of the clock pulse lp latch pulse input pin for display data " data is latched on the falling edge of the clock pulse l/r direction selection pin for reading display data " when set to v ss level "l", data is read sequentially from y240 to y1 " when set to v dd level "h", data is read sequentially from y1 to y240 dispoff control input pin for output deselect level " the input signal is level-shifted from the logic voltage level to the lcd driver voltage level, and controls the lcd driver circuit. " when set to v ss level ?l?, the lcd driver output pins (y1-y240) are set to level v 5 " when dispoff is set to ?l?, the contents of the line latch are reset, but the display data in the data latch are read regardless of the condition of dispoff . when the dispoff function is canceled, the driver outputs deselect level (v 12 or v 43 ), then outputs the contents of the date latch onto the next falling edge of the lp. at that time, if the dispoff removal time can not keep regulation with what is shown on the ac characteristics, then it can not output the reading data correctly. fr ac signal input for lcd driving waveform " the input signal is level-shifted from the logic voltage level to the driver voltage level and controls the lcd driver circuit. " it normally inputs a frame inversion signal the lcd driver output pin?s output voltage level can be set to the line latch output signal and the fr signal md mode selection pin " when set to v ss level ?l?, 8-bit parallel input mode is set " when set to v dd level ?h", 4-bit parallel input mode is set nt7704 7 segment mode continued symbol function s/c segment mode/common mode selection pin " when set to v dd level "h", segment mode is set " when set to v ss level "l", common mode is set eio 1 , eio 2 input/output pin for chip selection " when l/r input is at v ss level ?l?, eio 1 is set for output, and eio 2 is set for input " when l/r input is at v dd level ?h?, eio 1 is set for input, and eio 2 is set for output " during output, it is set to ?h? while lp* xck is ?h? and then after 240-bits of data have been read, it is set to ?l? for one cycle (from falling edge to falling edge of xck), after which it returns to ?h? " during input, after the lp signal is input, the chip is selected while ei is set to ?l?. after 240-bits of data have been read, the chip is deselected y 1 - y 240 lcd driver output pins these correspond directly to each bit of the data latch, one level (v 0 , v 12 , v 43 , or v 5 ) is selected and output common mode symbol function v dd logic system power supply pin connects to +2.5 to +5.5v v ss ground pin connects to 0v v 0r , v 0l v 12r , v 12l v 43r , v 43l v 5r , v 5l power supply pin for lcd driver voltage bias. " normally, the bias voltage used is set by a resistor divider " ensure the voltages are set such that v ss v 5 nt7704 9 functional description 1. block description 1.1 active control in segment mode, it controls the selection or deselection of the chip. following a lp signal input, and after the select signal is input, a select signal is generated internally until 240 bits of data have been read in. once data input has been completed, a select signal for cascade connection is output, and the chip is deselected. in common mode, it controls the input/output data of the bi- directional pins. 1.2. sp conversion & data control in segment mode, it keeps input data which are 2 clocks of xck at 4-bit parallel mode into latch circuit, or keeps input data which are 1 clock of xck at 8-bit parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. 1.3. data latch control in segment mode, it selects the state of the data latch, which reads in the data bus signals. the shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit. 1.4. data latch in segment mode, it latches the data on the data bus. the latched state of each lcd driver output pin is controlled by the control logic and the data latch control. 240 bits of data are read in 20 sets of 8 bits. 1.5. line latch/shift register in segment mode, it ensures all 240 bits which have been read into the data latch, are simultaneously latched on to the falling edge of the lp signal, and output to the level shift block. in common mode, it shifts data from the data input pin on to the falling edge of the lp signal. 1.6. level shifter it ensures the logic voltage signal is level-shifted to the lcd driver voltage level, and output to the driver block. 1.7. 4-level driver it drives the lcd driver output pins from the line latch/shift register data, selecting one of 4 levels (v 0 , v 12 , v 43 , v 5 ) based on the s/c, fr and dispoff signals. 1.8. control logic controls the operation of each block. in segment mode, when an lp signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is deselected. in common mode, it controls the direction of data shift. nt7704 10 2. lcd driver output voltage level the relationship between the data bus signal, ac converted signal fr and lcd driver output voltage is as shown in the table below: 2.1. segment mode fr latch data dispoff driver output voltage level (y 1 - y 240 ) llh v 43 lhh v 5 hlh v 12 hhh v 0 xxl v 5 here, v ss v 5 < v 43 < v 12 < v 0 , h: v dd (+2.5 to +5.5v), l: v ss (0v), x: don't care 2.2. common mode fr latch data dispoff driver output voltage level (y 1 - y 240 ) llh v 43 lhh v 0 hlh v 12 hhh v 5 xxl v 5 here, v ss v 5 < v 43 < v 12 < v 0 , h: v dd (+2.5 to +5.5v), l: v ss (0v), x: don't care note: there are two kinds of power supply (logic level voltage, lcd driver voltage) for the lcd driver. please supply regular voltage which is assigned by specification for each power pin. that time "don't care" should be fixed to "h" or "l", avoiding floating. nt7704 11 3. relationship between the display data and driver output pins 3.1. segment mode: (a) 4-bit parallel mode number of clock md l/r eio 1 eio 2 data input 60clock 59clock 58clcok ~ 3clock 2clock 1clock d 0 y1 y5 y9 ~ y229 y233 y237 d 1 y2 y6 y10 ~ y230 y234 y238 d 2 y3 y7 y11 ~ y231 y235 y239 h l output input d 3 y4 y8 y12 ~ y232 y236 y240 d 0 y240 y236 y232 ~ y12 y8 y4 d 1 y239 y235 y231 ~ y11 y7 y3 d 2 y238 y234 y230 ~ y10 y6 y2 h h input output d 3 y237 y233 y229 ~ y9 y5 y1 (b) 8-bit parallel mode number of clock md l/r eio 1 eio 2 data input 30clock 29clock 28clcok ~ 3clock 2clock 1clock d 0 y1 y9 y17 ~ y217 y225 y233 d 1 y2 y10 y18 ~ y218 y226 y234 d 2 y3 y11 y19 ~ y219 y227 y235 d 3 y4 y12 y20 ~ y220 y228 y236 d 4 y5 y13 y21 ~ y221 y229 y237 d 5 y6 y14 y22 ~ y222 y230 y238 d 6 y7 y15 y23 ~ y223 y231 y239 l l output input d 7 y8 y16 y24 ~ y224 y232 y240 d 0 y240 y232 y224 ~ y24 y16 y8 d 1 y239 y231 y223 ~ y23 y15 y7 d 2 y238 y230 y222 ~ y22 y14 y6 d 3 y237 y229 y221 ~ y21 y13 y5 d 4 y236 y228 y220 ~ y20 y12 y4 d 5 y235 y227 y219 ~ y19 y11 y3 d 6 y234 y226 y218 ~ y18 y10 y2 l h input output d 7 y233 y225 y217 ~ y17 y9 y1 nt7704 12 3.2. common mode md l/r data transfer direction eio 1 eio 2 d 7 l (shift to left) y240 to y1 output input x l (single) h (shift to right) y1 to y240 input output x l (shift to left) y240 to y121 y120 to y1 output input input h (dual) h (shift to right) y1 to y120 y121 to y240 input output input here, l: v ss (0v), h: v dd (+2.5v to +5.5v), x: don't care note: "don't care" should be fixed to "h" or "l", avoiding floating. nt7704 13 4. connection examples of segment drivers 4.1. case of l/r = ?l? xck lp md fr d0 - d7 l/r eio1 eio2 xck lp md fr d0 - d7 l/r eio1 eio2 xck lp md fr d0 - d7 l/r eio1 eio2 xck lp md d0 - d7 fr v ss y240 ---------------------->y1 y240 ----------------------->y1 y240 ---------------------->y1 (data taking flow) first data last data /8 4.2. case of l/r = ?h? xck lp md d0 - d7 fr v dd y1 ---------------------->y240 (data taking flow) first data y1 ---------------------->y240 y1 ---------------------->y240 last data xck lp md fr d0 - d7 l/r eio1 eio2 xck lp md fr d0 - d7 l/r eio1 eio2 xck lp md fr d0 - d7 l/r eio1 eio2 v ss /8 nt7704 14 5. timing waveform of 4-device cascade connection of segment drivers n12 n12 n12 n12 n12 device a device b device c device d first data last data fr lp xck d0~d7 ei (device a) eo (device a) eo (device b) eo (device c) n: 4-bit parallel mode 60 8-bit parallel mode 30 h l nt7704 15 6. connection examples for common drivers d v ss (v dd ) v ss v ss fr first lp dispoff cs eio1 eio2 lp d7 md l/r fr dispoff y240 y1 cs last eio1 eio2 lp d7 md l/r fr dispoff y240 y1 cs eio1 eio2 lp d7 md l/r fr dispoff y240 y1 cs single mode (shifting towards the left) d v ss (v dd ) v ss v dd fr first lp dispoff y240 y1 last eio1 eio2 lp d7 md l/r fr dispoff eio1 eio2 lp d7 md l/r fr dispoff y240 y1 eio1 eio2 lp d7 md l/r fr dispoff y240 y1 single mode (sifting towards the right) nt7704 16 d1 eio1 eio2 lp d7 md l/r fr dispoff y240 y1 eio1 eio2 lp d7 md l/r fr dispoff y240 y1 eio1 eio2 lp d7 md l/r fr dispoff y240 y1 v ss (v dd ) v dd v ss fr lp dispoff d2 last2 first1 last1 first2 y121 y120 dual mode (shifting towards the left) d1 y240 y1 eio1 eio2 lp d7 md l/r fr dispoff eio1 eio2 lp d7 md l/r fr dispoff eio1 eio2 lp d7 md l/r fr dispoff y240 y1 v ss (v dd ) v dd v dd fr lp dispoff d2 last2 first1 last1 first2 y240 y1 y121 y120 dual mode (shifting towards the right) nt7704 17 7. precaution be careful when connecting or disconnecting the power this lsi has a high-voltage lcd driver, so it may be permanently damaged by a high current, which may occur if voltage is supplied to the lcd driver power supply while the logic system power supply is floating. the details are as follows: ! when connecting the power supply, connect the lcd driver power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lcd driver power. ! we recommend that you connect a serial resistor (50-100 ? ) or fuse to the lcd driver power v 0 of the system as a current limiting device. also, set a suitable value of the resistor in consideration of lcd display grade. in addition, when connecting the logic power supply, the logic condition of the lsi inside is insecure. therefore, connect the lcd driver power supply only after resetting the logic condition of this lsi inside to the dispoff function. after that, the dispoff cancel the function after the lcd driver power supply has become stable. furthermore, when disconnecting the power, set the lcd driver output pins to level v 5 on the dispoff function. after that, disconnect the logic system power after disconnecting the lcd driver power. when connecting the power supply, follow the recommended sequence shown. v dd v dd v ss dispoff v 0 v dd v ss v ss v 0 nt7704 18 absolute maximum rating* dc supply voltage v dd . . . . . . . . . . . . . -0.3v to +7.0v dc supply voltage v 0 . . . . . . . . . . . . . . -0.3v to +30v input voltage . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v operating ambient temperature . . . . -30 c to +85 c storage temperature . . . . . . . . . . . . .-45 c to +125 c * comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics dc characteristics segment mode (v ss = v 5 = 0v, v dd = 2.5 - 5.5v, v 0 = 15 to 30 v, and t a = -30 to +85 c, unless otherwise noted) parameter symbol min. typ. max. unit condition operating voltage 1 v dd 2.5 - 5.5 v operating voltage 2 v 0 15 - 30 v input high voltage v ih 0.8 v dd --v input low voltage v il - - 0.2 v dd v d0 - 7, xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , dispoff pins output high voltage v oh v dd - 0.4 - - v eio 1 , eio 2 pins, i oh = -0.4ma output low voltage v ol - - +0.4 v eio 1 , eio 2 pins, i ol = +0.4ma input leakage current 1 i ih --+1.0 a d0 - 7, xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , dispoff pins, v i = v dd input leakage current 2 i il ---1.0 a d0 - 7, xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , dispoff pins, v i = v ss - 1.5 2.0 v0 = +30.0v output resistance r on -2.02.5 k ? v0 = +20.0v y 1 - y 240 pins, n o v ? = 0.5v stand-by current i sb --10 a v ss pin, note 1 consumed current (1) (deselection) i dd1 --2mav dd pin, note 2 consumed current (2) (selection) i dd2 --12mav dd pin, note 3 consumed current i 0 --1.5mav 0 pin, note 4 note: 1. v dd = +5.0v, v 0 = +30v, v i = v ss 2. v dd = +5.0v, v 0 = +30v, f xck = 20mhz, no-load, ei = v dd the input data is turned over by the data taking clock (4-bit parallel input mode) 3. v dd = +5.0v, v 0 = +30v, f xck = 20mhz, no-load. ei = v ss the input data is turned over by the data taking clock (4-bit parallel input mode) 4. v dd = +5.0v, v 0 = +30v, f xck = 20mhz, f lp = 41.6khz. f fr = 80 hz, no-load the input data is turned over by the data taking clock (4-bit parallel-input mode) nt7704 19 common mode (v ss = v 5 = 0v, v dd = 2.5 - 5.5v, v 0 = 15 to 30 v, and t a = -30 to +85 c, unless otherwise noted) parameter symbol min. typ. max. unit condition operating voltage v dd 2.5 - 5.5 v operating voltage v 0 15 -30v input high voltage v ih 0.8 v dd --v input low voltage v il - - 0.2 v dd v d0 - 7, xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , dispoff pins output high voltage v oh v dd - 0.4 - - v eio 1 , eio 2 pins, i oh = -0.4ma output low voltage v ol - - +0.4 v eio 1 , eio 2 pins, i ol = +0.4ma input leakage current 1 i ih --+1.0 a d0 - 6, lp, l/r, fr, md, s/c and dispoff pins, v i = v dd input leakage current 2 i il ---1.0 a d0 - 7, xck, lp, l/r, fr, md, s/c, eio1, eio2, dispoff pins, v i = v ss input pull down current i pd - - 100 a xck, eio 1 , eio 2 , d7 pins - 1.5 2.0 v0 = +30.0v output resistance r on -2.02.5 k ? v0 = +20.0v y 1 - y 240 pins, n o v ? = 0.5v stand-by current i sb --10 a v ss pin, note 1 consumed current (1) i dd - - 120 a v dd pin, note 2 consumed current (2) i 0 - - 240 a v 0 pin, note 2 note: 1. v dd = +5.0v, v 0 = +30.0v, v i = v ss 2. v dd = +5.0v, v 0 = +30.0v, f lp = 41.6khz, f fr = 80hz, case of 1/480 duty operation, no-load nt7704 20 ac characteristics segment mode 1 (v ss = v 5 = 0v, v dd = 4.5 - 5.5v, v 0 = 15 to 30v, and t a = -30 to +85 c, unless otherwise noted) parameter symbol min. typ. max. unit condition shift clock period t wck 50 - ns tr, tf 10ns, note 1 shift clock "h" pulse width t wckh 15 - ns shift clock "l" pulse width t wckl 15 - ns data setup time t ds 10 - ns data hole time t dh 12 - ns latch pulse "h" pulse width t wlph 15 - ns shift clock rise to latch pulse rise time t ld 0- ns shift clock fall to latch pulse fall time t sl 30 - ns latch pulse rise to shift clock rise time t ls 25 - ns latch pulse fall to shift clock rise time t lh 25 - ns input signal rise time t r - 50 ns note 2 input signal fall time t f - 50 ns note 2 enable setup time t s 10 - ns dispoff removal time t sd 100 - ns dispoff enable pulse width t wdl 1.2 - s output delay time (1) t d - 30 ns cl = 15pf output delay time (2) t pd1 , t pd2 -1.2 s cl = 15pf output delay time (3) t pd3 -1.2 s cl = 15pf note: 1. take the cascade connection into consideration. 2. (t ck -t wckii -t wckl )/2 is the maximum in the case of high speed operation. nt7704 21 segment mode 2 (v ss = v 5 = 0v, v dd = 3.0 - 4.5v, v 0 = 15 to 30v, and t a = -30 to +85 c, unless otherwise noted) parameter symbol min. typ. max. unit condition shift clock period t wck 66 - ns tr, tf 10ns, note 1 shift clock "h" pulse width t wckh 23 - ns shift clock "l" pulse width t wckl 23 - ns data setup time t ds 15 - ns data hole time t dh 23 - ns latch pulse "h" pulse width t wlph 30 - ns shift clock rise to latch pulse rise time t ld 0- ns shift clock fall to latch pulse fall time t sl 50 - ns latch pulse rise to shift clock rise time t ls 30 - ns latch pulse fall to shift clock fall time t lh 30 - ns input signal rise time t r - 50 ns note 2 input signal fall time t f - 50 ns note 2 enable setup time t s 15 - ns dispoff removal time t sd 100 - ns dispoff enable pulse width t wdl 1.2 - s output delay time (1) t d - 41 ns cl = 15pf output delay time (2) t pd1 , t pd2 -1.2 s cl = 15pf output delay time (3) t pd3 -1.2 s cl = 15pf note: 1. take the cascade connection into consideration. 2. (t ck -t wckii -t wckl )/2 is the maximum in the case of high speed operation. nt7704 22 segment mode 3 (v ss = v 5 = 0v, v dd = 2.5 - 3.0v, v 0 = 15 to 30v, and t a = -30 to +85 c, unless otherwise noted) parameter symbol min. typ. max. unit condition shift clock period t wck 82 - ns tr, tf 10ns, note 1 shift clock "h" pulse width t wckh 28 - ns shift clock "l" pulse width t wckl 28 - ns data setup time t ds 20 - ns data hole time t dh 23 - ns latch pulse "h" pulse width t wlph 30 - ns shift clock rise to latch pulse rise time t ld 0- ns shift clock fall to latch pulse fall time t sl 65 - ns latch pulse rise to shift clock rise time t ls 30 - ns latch pulse fall to shift clock fall time t lh 30 - ns input signal rise time t r - 50 ns note 2 input signal fall time t f - 50 ns note 2 enable setup time t s 15 - ns dispoff removal time t sd 100 - ns dispoff enable pulse width t wdl 1.2 - s output delay time (1) t d - 57 ns cl = 15pf output delay time (2) t pd1 , t pd2 -1.2 s cl = 15pf output delay time (3) t pd3 -1.2 s cl = 15pf note: 1. take the cascade connection into consideration. 2. (t ck -t wckii -t wckl )/2 is the maximum in the case of high speed operation. nt7704 23 timing waveform of the segment mode tsl lp last data top data tld tls twckl tr tr twck tds tdh xck d0 - d7 dispoff tlh twdl tsd twlph twckh tpd1 tpd2 tpd3 fr lp y1 - y240 dispoff xck eo ts 12 td n: 4-bit parallel mode 60 8-bit parallel mode 30 lp ei n nt7704 24 common mode (v ss = v 5 = 0v, v dd = 2.5 - 5.5v, v 0 = 15 to 30v and t a = -30 to +85 c, unless otherwise noted) parameter symbol min. typ. max. unit condition shift clock period t wlp 250 - - ns t r , t f 20ns 15 - - ns v dd = +5.0v 10% shift clock "h" pulse width t wlph 30 - - ns v dd = +2.5 - +4.5v data setup time t su 30 - - ns data hole time t h 50 - - ns input signal rise time t r -50ns input signal fall time t f -50ns dispoff removal time t sd 100 - - ns dispoff enable pulse width t wdl 1.2 - - s output delay time (1) t dl - - 200 ns c l = 15pf output delay time (2) t pd1 , t pd2 --1.2 s c l = 15pf output delay time (3) t pd3 --1.2 s c l = 15pf nt7704 25 timing characteristics of common mode tr tf lp dispoff twdl tsd twlp twlph tsu th tdl eio2 (di7) eio1 tpd1 tpd2 tpd3 fr lp y1 - y240 dispoff nt7704 26 application circuit (for reference only) yd c o m 1 c o m 2 c o m 3 c o m 4 7 9 c o m 4 8 0 seg1 seg2 seg3 seg960 seg959 lcd controller /8 fr lp xck eio1 md s/c l/r d0 - d7 eio2 fr lp xck eio1 md s/c l/r d0 - d7 eio2 fr lp xck eio1 md s/c l/r d0 - d7 eio2 fr lp xck eio1 md s/c l/r d0 - d7 eio2 /8 y1 - y240 y1 - y240 y1 - y240 y1 - y240 /5 /5 fr lp xck xd 0 - xd 7 dispoff v ss (case of 1/n bias) nt7704*4 nt7704*2 960*480 dot matrix lcd panel dispoff dispoff dispoff dispoff v dd v 5 v 1 v 2 v 3 4 v (n-4)r r r r r v 0 v 0 v ss note: v 0 -v 1 >1.5v fr lp xck eio1 md s/c l/r d0 - d7 eio2 dispoff y1 - y240 fr lp xck eio1 md s/c l/r eio2 dispoff y1 - y240 d0 - d7 nt7704 27 bonding diagram nt7704 12968um 1168um 1 x alk_l x x alk_r x x dummy pad x 208 209 224 225 432 433 448 ( 0 , 0 ) x y x pad location pad no. designation x y pad no. designation x y 1v 0l -6220 -521 31 v 5l -4410 -521 2v 0l -6150 -521 32 v 5l -4350 -521 3v 0l -6090 -521 33 v 5l -4290 -521 4v 0l -6030 -521 34 v 5l -4230 -521 5v 0l -5970 -521 35 v 5l -4170 -521 6v 0l -5910 -521 36 v 5l -4110 -521 7v 0l -5850 -521 37 v 5l -4050 -521 8v 0l -5790 -521 38 v 5l -3990 -521 9v 0l -5730 -521 39 v 5l -3930 -521 10 v 0l -5670 -521 40 v 5l -3870 -521 11 v 0l -5610 -521 41 v ss -3810 -521 12 v 0l -5550 -521 42 v ss -3750 -521 13 v 12l -5490 -521 43 v ss -3690 -521 14 v 12l -5430 -521 44 v ss -3630 -521 15 v 12l -5370 -521 45 v ss -3570 -521 16 v 12l -5310 -521 46 v ss -3510 -521 17 v 12l -5250 -521 47 v ss -3450 -521 18 v 12l -5190 -521 48 v ss -3390 -521 19 v 12l -5130 -521 49 v ss -3330 -521 20 v 12l -5070 -521 50 v ss -3270 -521 21 v 43l -5010 -521 51 v ss -3210 -521 22 v 43l -4950 -521 52 v ss -3150 -521 23 v 43l -4890 -521 53 v ss -3090 -521 24 v 43l -4830 -521 54 v ss -3030 -521 25 v 43l -4770 -521 55 v ss -2970 -521 26 v 43l -4710 -521 56 v ss -2910 -521 27 v 43l -4650 -521 57 v ss -2850 -521 28 v 43l -4590 -521 58 v ss -2790 -521 29 v 5l -4530 -521 59 v ss -2730 -521 30 v 5l -4470 -521 60 v ss -2670 -521 nt7704 28 pad location (continued) pad no. designation x y pad no. designation x y 61 v ss -2610 -521 101 d1 -210 -521 62 v ss -2550 -521 102 d1 -150 -521 63 v ss -2490 -521 103 d1 -90 -521 64 v ss -2430 -521 104 d2 -30 -521 65 v ss -2370 -521 105 d2 30 -521 66 v ss -2310 -521 106 d2 90 -521 67 v dd -2250 -521 107 d3 150 -521 68 v dd -2190 -521 108 d3 210 -521 69 v dd -2130 -521 109 d3 270 -521 70 v dd -2070 -521 110 d4 330 -521 71 v dd -2010 -521 111 d4 390 -521 72 v dd -1950 -521 112 d4 450 -521 73 v dd -1890 -521 113 d5 510 -521 74 v dd -1830 -521 114 d5 570 -521 75 v dd -1770 -521 115 d5 630 -521 76 v dd -1710 -521 116 d6 690 -521 77 v dd -1650 -521 117 d6 750 -521 78 v dd -1590 -521 118 d6 810 -521 79 v dd -1530 -521 119 d7 870 -521 80 v dd -1470 -521 120 d7 930 -521 81 v dd -1410 -521 121 d7 990 -521 82 v dd -1350 -521 122 xck 1050 -521 83 v dd -1290 -521 123 xck 1110 -521 84 v dd -1230 -521 124 xck 1170 -521 85 v dd -1170 -521 125 dispoff 1230 -521 86 v dd -1110 -521 126 dispoff 1290 -521 87 v dd -1050 -521 127 dispoff 1350 -521 88 v dd -990 -521 128 lp 1410 -521 89 v dd -930 -521 129 lp 1470 -521 90 v dd -870 -521 130 lp 1530 -521 91 v dd -810 -521 131 eio 1 1590 -521 92 v dd -750 -521 132 eio 1 1650 -521 93 s/c -690 -521 133 eio 1 1710 -521 94 s/c -630 -521 134 fr 1770 -521 95 eio 2 -570 -521 135 fr 1830 -521 96 eio 2 -510 -521 136 fr 1890 -521 97 eio 2 -450 -521 137 l/r 1950 -521 98 d0 -390 -521 139 l/r 2010 -521 99 d0 -330 -521 139 l/r 2070 -521 100 d0 -270 -521 140 md 2130 -521 nt7704 29 pad location (continued) pad no. designation x y pad no. designation x y 141 md 2190 -521 181 v 43r 4590 -521 142 md 2250 -521 182 v 43r 4650 -521 143 v ss 2310 -521 183 v 43r 4710 -521 144 v ss 2370 -521 184 v 43r 4770 -521 145 v ss 2430 -521 185 v 43r 4830 -521 146 v ss 2490 -521 186 v 43r 4890 -521 147 v ss 2550 -521 187 v 43r 4950 -521 148 v ss 2610 -521 188 v 43r 5010 -521 149 v ss 2670 -521 189 v 12r 5070 -521 150 v ss 2730 -521 190 v 12r 5130 -521 151 v ss 2790 -521 191 v 12r 5190 -521 152 v ss 2850 -521 192 v 12r 5250 -521 153 v ss 2910 -521 193 v 12r 5310 -521 154 v ss 2970 -521 194 v 12r 5370 -521 155 v ss 3030 -521 195 v 12r 5430 -521 156 v ss 3090 -521 196 v 12r 5490 -521 157 v ss 3150 -521 197 v 0r 5550 -521 158 v ss 3210 -521 198 v 0r 5610 -521 159 v ss 3270 -521 199 v 0r 5670 -521 160 v ss 3330 -521 200 v 0r 5730 -521 161 v ss 3390 -521 201 v 0r 5790 -521 162 v ss 3450 -521 202 v 0r 5850 -521 163 v ss 3510 -521 203 v 0r 5910 -521 164 v ss 3570 -521 204 v 0r 5970 -521 165 v ss 3630 -521 205 v 0r 6030 -521 166 v ss 3690 -521 206 v 0r 6090 -521 167 v ss 3750 -521 207 v 0r 6150 -521 168 v ss 3810 -521 208 v 0r 6220 -521 169 v 5r 3870 -521 209 y1 6430 -450 170 v 5r 3930 -521 210 y2 6430 -390 171 v 5r 3990 -521 211 y3 6430 -330 172 v 5r 4050 -521 212 y4 6430 -270 173 v 5r 4110 -521 213 y5 6430 -210 174 v 5r 4170 -521 214 y6 6430 -150 175 v 5r 4230 -521 215 y7 6430 -90 176 v 5r 4290 -521 216 y8 6430 -30 177 v 5r 4350 -521 217 y9 6430 30 178 v 5r 4410 -521 218 y10 6430 90 179 v 5r 4470 -521 219 y11 6430 150 180 v 5r 4530 -521 220 y12 6430 210 nt7704 30 pad location (continued) pad no. designation x y pad no. designation x y 221 y13 6430 270 261 y53 4050 529 222 y14 6430 330 262 y54 3990 529 223 y15 6430 390 263 y55 3930 529 224 y16 6430 450 264 y56 3870 529 225 y17 6210 529 265 y57 3810 529 226 y18 6150 529 266 y58 3750 529 227 y19 6090 529 267 y59 3690 529 228 y20 6030 529 268 y60 3630 529 229 y21 5970 529 269 y61 3570 529 230 y22 5910 529 270 y62 3510 529 231 y23 5850 529 271 y63 3450 529 232 y24 5790 529 272 y64 3390 529 233 y25 5730 529 273 y65 3330 529 234 y26 5670 529 274 y66 3270 529 235 y27 5610 529 275 y67 3210 529 236 y28 5550 529 276 y68 3150 529 237 y29 5490 529 277 y69 3090 529 238 y30 5430 529 278 y70 3030 529 239 y31 5370 529 279 y71 2970 529 240 y32 5310 529 280 y72 2910 529 241 y33 5250 529 281 y73 2850 529 242 y34 5190 529 282 y74 2790 529 243 y35 5130 529 283 y75 2730 529 244 y36 5070 529 284 y76 2670 529 245 y37 5010 529 285 y77 2610 529 246 y38 4950 529 286 y78 2550 529 247 y39 4890 529 287 y79 2490 529 248 y40 4830 529 288 y80 2430 529 249 y41 4770 529 289 y81 2370 529 250 y42 4710 529 290 y82 2310 529 251 y43 4650 529 291 y83 2250 529 252 y44 4590 529 292 y84 2190 529 253 y45 4530 529 293 y85 2130 529 254 y46 4470 529 294 y86 2070 529 255 y47 4410 529 295 y87 2010 529 256 y48 4350 529 296 y88 1950 529 257 y49 4290 529 297 y89 1890 529 258 y50 4230 529 298 y90 1830 529 259 y51 4170 529 299 y91 1770 529 260 y52 4110 529 300 y92 1710 529 nt7704 31 pad location (continued) pad no. designation x y pad no. designation x y 301 y93 1650 529 341 y133 -750 529 302 y94 1590 529 342 y134 -810 529 303 y95 1530 529 343 y135 -870 529 304 y96 1470 529 344 y136 -930 529 305 y97 1410 529 345 y137 -990 529 306 y98 1350 529 346 y138 -1050 529 307 y99 1290 529 347 y139 -1110 529 308 y100 1230 529 348 y140 -1170 529 309 y101 1170 529 349 y141 -1230 529 310 y102 1110 529 350 y142 -1290 529 311 y103 1050 529 351 y143 -1350 529 312 y104 990 529 352 y144 -1410 529 313 y105 930 529 353 y145 -1470 529 314 y106 870 529 354 y146 -1530 529 315 y107 810 529 355 y147 -1590 529 316 y108 750 529 356 y148 -1650 529 317 y109 690 529 357 y149 -1710 529 318 y110 630 529 358 y150 -1770 529 319 y111 570 529 359 y151 -1830 529 320 y112 510 529 360 y152 -1890 529 321 y113 450 529 361 y153 -1950 529 322 y114 390 529 362 y154 -2010 529 323 y115 330 529 363 y155 -2070 529 324 y116 270 529 364 y156 -2130 529 325 y117 210 529 365 y157 -2190 529 326 y118 150 529 366 y158 -2250 529 327 y119 90 529 367 y159 -2310 529 328 y120 30 529 368 y160 -2370 529 329 y121 -30 529 369 y161 -2430 529 330 y122 -90 529 370 y162 -2490 529 331 y123 -150 529 371 y163 -2550 529 332 y124 -210 529 372 y164 -2610 529 333 y125 -270 529 373 y165 -2670 529 334 y126 -330 529 374 y166 -2730 529 335 y127 -390 529 375 y167 -2790 529 336 y128 -450 529 376 y168 -2850 529 337 y129 -510 529 377 y169 -2910 529 338 y130 -570 529 378 y170 -2970 529 339 y131 -630 529 379 y171 -3030 529 340 y132 -690 529 380 y172 -3090 529 nt7704 32 pad location (continued) pad no. designation x y pad no. designation x y 381 y173 -3150 529 416 y208 -5250 529 382 y174 -3210 529 417 y209 -5310 529 383 y175 -3270 529 418 y210 -5370 529 384 y176 -3330 529 419 y211 -5430 529 385 y177 -3390 529 420 y212 -5490 529 386 y178 -3450 529 421 y213 -5550 529 387 y179 -3510 529 422 y214 -5610 529 388 y180 -3570 529 423 y215 -5670 529 389 y181 -3630 529 424 y216 -5730 529 390 y182 -3690 529 425 y217 -5790 529 391 y183 -3750 529 426 y218 -5850 529 392 y184 -3810 529 427 y219 -5910 529 393 y185 -3870 529 428 y220 -5970 529 394 y186 -3930 529 429 y221 -6030 529 395 y187 -3990 529 430 y222 -6090 529 396 y188 -4050 529 431 y223 -6150 529 397 y189 -4110 529 432 y224 -6210 529 398 y190 -4170 529 433 y225 -6430 450 399 y191 -4230 529 434 y226 -6430 390 400 y192 -4290 529 435 y227 -6430 330 401 y193 -4350 529 436 y228 -6430 270 402 y194 -4410 529 437 y229 -6430 210 403 y195 -4470 529 438 y230 -6430 150 404 y196 -4530 529 439 y231 -6430 90 405 y197 -4590 529 440 y232 -6430 30 406 y198 -4650 529 441 y233 -6430 -30 407 y199 -4710 529 442 y234 -6430 -90 408 y200 -4770 529 443 y235 -6430 -150 409 y201 -4830 529 444 y236 -6430 -210 410 y202 -4890 529 445 y237 -6430 -270 411 y203 -4950 529 446 y238 -6430 -330 412 y204 -5010 529 447 y239 -6430 -390 413 y205 -5070 529 448 y240 -6430 -450 414 y206 -5130 529 alk_l -6318 -533 415 y207 -5190 529 alk_r 6318 -533 nt7704 33 dummy pad location (total: 6 pin) no. x y no. x y 1 6430 -520 4 -6280 529 2 6430 520 5 -6430 520 3 6280 529 6 -6430 -520 nt7704 34 package information a1 a2 d1 d2 n1 m1 a1 a2 d1 c2 208 m1 n1 d2 c1 d1 c1 d1 n1 m1 16 n1 m1 h d2 c1 d1 c1 d1 n1 m1 16 n1 m1 h nt7704 b j d1 r r m2 n1 m2 4 n1 m2 m2 n1 2 m2 n1 m2 c3 m1 n2 76 m3 n2 m2 c3 d2 m1 n2 b j d1 d2 m3 m3 65 m1 n2 (l) 65 m1 n2 (r) chip outline dimensions unit: um symbol dimensions in um symbol dimensions in um a1 204 h 51 a2 54 j 166 b 264 m1 39 c1 64 m2 55 c2 55 m3 38 c3 63 n1 72 d1 70 n2 90 d2 60 r 35 nt7704 35 tcp pin layout nt7704 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dummy v0l v0l v12l v43l v5l vss vdd s/c eio2 d0 d1 d2 d3 d4 d5 d6 d7 lp eio1 fr l/r md nc vss nc v5r v43r dispoff xck 31 32 v12r v0r v0r dummy 33 34 35 36 37 dummy y1 y2 y4 y3 y5 268 269 270 271 272 y236 y237 y238 y239 y240 dummy 151 152 153 154 150 155 y118 y119 y120 y122 y121 y123 (copper side view) nt7704 36 external view of tcp pins n t7704h - tabf4 nt7704 37 cautions concerning storage: 1. when storing the product, it is recommended that it be left in its shipping package. after the seal of the packing bag has been broke, store the products in a nitrogen atmosphere. 2. storage conditions : storage state storage conditions unopened (less than 90 days) temperature: 5 to 30 ; humidity: 80%rh or less after seal of broken (less than 30 days) room temperature, dry nitrogen atmosphere 3. don't store in a location exposed to corrosive gas or excessive dust. 4. don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. don't store the product such that it is subjected to an excessive load weight, such as by stacking. 6. deterioration of the plating may occur after long-term storage, so special care is required. it is recommended that the products be inspected before use. nt7704 38 tray information a e f w2 w1 t1 t2 section x-x b yy 4 25=100 h g e f t1 t2 w2 section y-y d c h g w1 xx h30-523 59-25 tray outline dimensions unit: mm symbol dimensions in mm symbol dimensions in mm a 1.30 g 0.64 b 2.67 h 4.20 c 13.30 w1 76.0 d 16.26 w2 68.0 e 1.60 t1 71.0 f 1.40 t2 68.3 nt7704 39 ordering information part no. package NT7704H-BDT au bump on chip tray nt7704h-tabf4 tcp form nt7704 40 product spec. change notice nt7704 specification revision history version content date 1.0 tcp and tray information addition (page 36-39) dec. 2001 0.2 gold bump size revision (page 34) m1: 45 39, m2: 58 55 sep. 2001 0.1 pad location addition nov. 2000 0.0 original nov. 2000 |
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